The most commonly used bias circuits for bipolar transistors, such as current mirrors for temperature compensation, require two or more bipolar transistors in series. At very low operating voltages, the voltage drop across two emitter-base junctions of the two bipolar transistors in series may be large enough relative to the available voltage supply that such bias circuits become inoperable. The excessive voltage drop problem may be overcome by coupling a bipolar transistor in series with a field effect transistor, referred to herein as a low-control-voltage transistor, having a control voltage less than the emitter-base turn-on voltage of the bipolar transistor. However, none of the existing techniques for accomplishing such integration are cost-effective or practical for III-V semiconductors such as gallium arsenide (GaAs). A majority of the existing techniques require at least two distinct epitaxial growth steps with intervening wafer processing, making them prohibitively expensive for cost-sensitive applications. Furthermore, ion implantation is not practical for forming reliable p-n junctions in GaAs because gallium and arsenic vacancies and interstitials created by such ion implantation cannot be completely removed by a subsequent anneal, leaving high concentrations of deep-level traps in the GaAs.
Other existing integration techniques require significant wafer processing prior to an epitaxial growth step or steps, or are practical only for p-n-p bipolar transistors and n-channel junction field effect transistors. Such techniques are expensive, poorly reproducible, and incompatible with large segments of the transistor market. Accordingly, a need exists for a semiconductor component that integrates a bipolar transistor with a low-control-voltage transistor, in a package that meets market expectations and needs, and a need also exists for a cost-effective, practical method of manufacturing such a semiconductor component.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner.